Boring class.

Took it with TA Sam Lee
definitely made it easier for me!
GOAT

I took this class in Winter 2022, and it was really different from what you'd expect from a class. The class is entirely run by the TA. I didn't even see the professor once. Also, I don't know why we have to take this class. It's literally useless. You'll find that the projects aren't too hard, but you can get into trouble by running into 1000 problems with their outdated software. I had Samuel Lee for this class, who was extremely helpful and lenient. I talked to my friends from the other sections, and they mentioned that they were simply given the spec and instructed to read it themselves and do the projects. Sam studies all the projects and picks out parts that he thinks will be difficult for us, and he legit made an entire slide deck going over difficult concepts and how we should do the projects. He's also super reasonable, so if you go to his office hours and talk to him, he's likely to help you out. I give the class a 7/10 cause the class sucked, but the overall experience wasn't bad.

You should expect 4 labs. The first two labs are fairly easy. The third lab might wreck you, but if you go to office hours you can survive. The fourth lab is a project of your choice (HINT: CHOOSE AN EASY PROJECT GUYS).

Boring and useless class. But like what others said, a good TA (and parter) will save you tons of effort. The projects are fairly easy and the spec is mostly clear (unlike the shitty 152B). You can find past solutions online. Writing reports is tedious, time-consuming but not difficult. For the final project which you can make on your own, I suggest working on something simple, because a complicated one will not bring you much grade boost and will likely cause trouble.

Fuck this class. It's fucking useless.

I didn't learn anything from this class

This class made me never want to touch Verilog again, but the TAs are awesome.

This is an extremely time-consuming class. If you don't have a windows computer, you can't work on projects outside of class time/ office hours which is really annoying. Be as productive as possible during class time as possible.

This class is an entirely TA-run lab, and your grading is entirely dependent on your TA. I had Tang, who was goated. This class is doing 4 verilog labs, with the fourth being a final project. They're all basically based on completion, it just takes time and sucks to write Verilog. Pretty boring and useless class, had a cool lab partner which made it better.

Class is fun and easy albeit pretty useless.
Being good at M51A helps.

There isn't much guidance.