Class is fun and easy albeit pretty useless.
Being good at M51A helps.

There isn't much guidance.

This is a lab class taught entirely by the TA. We had four lab that were one in Verilog, with the last one being a large final project. Each lab had its own guide pdf for what to do. We followed those and the TA walked around the classroom being available for questions. Verilog is annoying and the labs are time-consuming, but my group (you work in groups for this class) was able to get everything done in class, only attending office hours once or twice.

(These ratings are for Tyler Albarran because this class is entirely run by TAs and not Majid)

Tyler is the best TA! Take this class with him if you can. He's very helpful and knowledgeable. Yes, there are lots of issues with this class, including the deprecated software and buggy hardware, but I actually greatly enjoyed taking his lab section.

All the labs 1-3 are very reasonable and can be done without external help or extra time outside of class. Lab 4 is where you create your own project and can not be completed in time without going to office hours. Be warned: there are huge lines, especially during the last week before the lab is due. People were waiting in the hallways for up to a few hours before Tyler implemented a policy to randomly kick out one lab group every 30 minutes.

Overall, not too bad, but the whole course is in serious need of a refresher.

shuwen qiu my queen

First off, this class is not with the professor listed - you will spend the entirety of it with an assigned TA. Also, you will spend the entirety of it with a partner/group that you will choose at the first lab section, so if you want to minimize the risk of being paired with a useless partner, I recommend you sign up for this class with a friend. In this class, you will be learning Verilog and implementing some designs on an FPGA (circuit board) in Verilog. It's a pretty cool class I thought, as you get to get hands-on experience and see what computers are capable of even at a low level, but it's knowledge that won't really be too useful if you're going the software engineering route. In terms of workload, my partner and I handled pretty much all of our workload in class in terms of getting the code done, however there are open lab hours which we used maybe once or twice to be sure we would finish an assignment on time (you need to be physically present with the FPGA for testing, so can't do any testing on your own machine). Apart from that, there are lab reports that you need to do, but these usually would not take more than 2-3 hours per report, and there were only 4 or 5 of them throughout the entirety of the quarter.

Somehow they still don't get rid of this class yet. I couldn't contribute much to my team because the instructions were always unclear and I didn't even know where to start every lab. I was lucky enough to have a smart partner who literally carried the whole team but I ended up finishing this class learning nothing. We spent hours outside of class to develop the final project and it was exhasting. Hope I don't have to see Verilog again even though I'm a CSE major.

My TA for this class was Weitong Zhang. He did a good job lecturing and going over the project specs.
The class consisted of four projects. Before each project, the TA would give a lecture going over the spec, and the rest of the sections were just office hours. The projects primarily consisted of manipulating clocks and building FSMs using Verilog. It wasn't too difficult, and mainly built off of concepts from CS M51A/ECE M16. The projects were due every 2-3 weeks, which is more than enough time to complete them.

Ok so this class was with a TA, and I had Weitong Zhang, who was very friendly and helpful. The class is honestly pretty easy: there is 1-2 lectures about the next project, then the rest of the sections are OH until the project is due. It was relaxed.

There are 4 labs. The labs got a little hard at the end, but mostly if you pay attention to the pre-lab and use good practice for clocking, then you're A-OK.
The "code" is all done in Verilog, which is actually a description language (like HTML is to webpages): it describes digital systems, but doesn't "code" more than define behavior on certain signals. I say this bc it's a little hard to grasp at first, but easy once you get the hang of it. I did all the projects in <15 hours. If you design your module correctly, write good test cases, and make a lab report with all the right components, you get an A.

I'm not gonna lie, I wasn't a huge fan of Verilog before taking this class, and I still am not a fan of it. But the lab itself wasn't super hard. There were four projects, each of which required a lab report and a 10-minute video explanation of your Verilog code. I ended up grinding out most of them the weekend they were due (projects were due every other Sunday night), and I got pretty good grades, to say the least. My TA was also a nice guy who explained concepts well and graded the projects leniently. Overall, taking this class in COVID was a bit boring since we didn't get to work with actual hardware, but it wasn't a tough class by any means.

The assignments in this class take almost as long as a 4-unit course. We had 4 assignments, each requiring a 10-ish page report and a 10-minute video with your narration of your implementation. Good thing was that the grading was rather lenient and my TA was very clear and helpful in discussions. There is no Piazza/forum (CCLE forum was barely ever monitored) so you have to get started early and questions need to be asked in person. Overall not a bad class if you understood the gist of M51A. Projects are essentially the Verilog version of things we learned in M51A, not many new concepts.