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- Miodrag Potkonjak
- COM SCI M152A
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Based on 9 Users
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Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
Grade distributions are collected using data from the UCLA Registrar’s Office.
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What a god awful class. Possibly the worst of the CS classes. Everythings outdated, the TAs don't know what they're doing, there's no real structure. You have to come in on your own to continuously debug the pieces of shit equipment. Long ass lab reports that are unnecessary. Just take the L.
This class is actually so terrible. The first couple projects are fairly reasonable but still require you to probably come to multiple office hours to complete them. Project 3 sucks and I spent a long time coding it outside of lab which is difficult since you only have access to the board you need in lab. So if you are like me and get a partner that does ABSOLUTELY NOTHING except mooch off you for 131 help and shows up to lab an hour late every day you are going to hate your life. Project 4 was the big one and the TA pushes you to do a hard project. Our group did probably the first or second hardest project in our lab class and produced a project with absolutely no bugs yet we got a peer grade of 8/10 which doesn't help in a class that curves down. I spent so many nights coding this dumb thing until 5 in the morning so I could go in tomorrow morning and get it to run on the board to see if it works. My partner sucked so much that when demo day came he didn't even know how to start and play the game we made. He made 0 commits to our shared github page. We got 60/60 for all 4 projects for the code portion and around a 34-36/40 on every report portion. So we got somewhere between 94-96% on EVERY PROJECT AND GOT CURVED DOWN. Class is bullshit and a waste of time. Don't kill yourself for 2 units like I did.
I am a CS student with 3.6 GPA. And this is the worst class I have taken at UCLA, period. For this quarter I took 4 classes, one GE, one elective, one algorithm, and this class. I spent about 35% of my time studied the rest of the three classes and got a grade above the average for all of them (at least for now). All the rest of my time was spent on this class and I do not even know if I could pass, I am considering not doing anything an just let it fail.
That is how bad this class is. When I was taking 35l I feel like it was hell, but now I would rather take another 10 quarter of 35l than taking one-quarter of this course. If you are looking for a class that is worse than cs35l, just take this class.
For cs35l it is possible to have a decent TA who could help you with the project. But for this class, TAs are NOT HELPFUL! Every time I ask about anything, he told me he did not know either. His lecture is basically reading the slides.
Lab 3 is extremely hard. More than half of the class did not finish it by the extended deadline. another thing which sucks about this class is, it requires special hardware that could only be accessed during the class, so if you can not figure it out during class time and office hours, you are doomed.
Overall, for this class, you get hard projects with a massive volume, little help from TA, little feedback from previous works, no extra resources to study. And the more you know software languages like java or python, the more you will probably be in trouble because hardware language works totally differently!
Finally, don't look at any comment that is earlier than mine. Because from this quarter they changed the requirement for the project. The project they used for last quarter is so easy compared to mine.
So, this class entirely depends on your TA. My TA was Hongxiang Gu. I think he's pretty fair in terms of grading the reports. It's good to start early. The guide they give about what the reports should be like definitely explain exactly what you need to write. We got 100% in all of the labs because we did the following:
- For every module, we described its functioning and name/explain how it interfaces with other modules and then drew a logic diagram
- For each module, we wrote something about how we tested it. If we didn't test it, we wrote a sentence or two about why we didn't (from a previous project, just looked if the hardware worked etc).
I think the TA just wanted a high level understanding of the architecture/design of the project.
My advice for the final project: Do not be too ambitious. Don't use a bunch of external hardware unless it's really well documented. Our project just used the FPGA board and the VGA output, we just added a bunch of features to make it good enough compared to the others.
Your grade depends on the curve, which sucks because it's a crapshoot depending on how good your class is.
Outside work: Me and my teammate did some of the coding/testbenches outside of lab, mainly because we were only 2 people. I know people who never needed to do work outside of lab.
I think the hardest lab was probably Lab 3, the stopwatch. To do well in that lab it's necessary to have a high level gameplan/design before you start coding. Make sure to use testbenches while you code, it's super useful for debugging and generally creating testbenches don't take too much time.
I got a raw score of 91.8% and got curved down to a B-. The other reviews are correct. This class is super BS. Although it is great being given the opportunity to write Verilog code in a more hands-on environment such as programming on an FPGA board, I learned nothing besides better Verilog programming. This class is just forgettable. I can even say this class is useless, considering you are not being rewarded for trying but rather create an artificial curve in a lab section as horrendous as physics labs. Got punished for trying very hard and doing well in the final project, but a few missteps and there goes your grade.
I am very very glad not that many classes are like this. I am just glad I passed this class in the 2 physics labs I have to take as a CSE major. This class is just terrible.
Pretty meh class. We did 4 projects using Verilog and fpga boards, and there was little instruction. Each project has a medium sized lab report component. The final project is open ended and worth 50% of your grade. The professor is not involved, so you better hope you get a cool TA like I had.
There is not enough lab time to complete the last project, so you need to go to several office hours to finish, which sucks.
Fairly easy and light class if you have decent lab partners.
The grading policy is unfortunately bullshit, with the average forced to a B- so everyone is curved down. We got >90% and got a B. The grading distributions of the past years no longer apply.
What a god awful class. Possibly the worst of the CS classes. Everythings outdated, the TAs don't know what they're doing, there's no real structure. You have to come in on your own to continuously debug the pieces of shit equipment. Long ass lab reports that are unnecessary. Just take the L.
This class is actually so terrible. The first couple projects are fairly reasonable but still require you to probably come to multiple office hours to complete them. Project 3 sucks and I spent a long time coding it outside of lab which is difficult since you only have access to the board you need in lab. So if you are like me and get a partner that does ABSOLUTELY NOTHING except mooch off you for 131 help and shows up to lab an hour late every day you are going to hate your life. Project 4 was the big one and the TA pushes you to do a hard project. Our group did probably the first or second hardest project in our lab class and produced a project with absolutely no bugs yet we got a peer grade of 8/10 which doesn't help in a class that curves down. I spent so many nights coding this dumb thing until 5 in the morning so I could go in tomorrow morning and get it to run on the board to see if it works. My partner sucked so much that when demo day came he didn't even know how to start and play the game we made. He made 0 commits to our shared github page. We got 60/60 for all 4 projects for the code portion and around a 34-36/40 on every report portion. So we got somewhere between 94-96% on EVERY PROJECT AND GOT CURVED DOWN. Class is bullshit and a waste of time. Don't kill yourself for 2 units like I did.
I am a CS student with 3.6 GPA. And this is the worst class I have taken at UCLA, period. For this quarter I took 4 classes, one GE, one elective, one algorithm, and this class. I spent about 35% of my time studied the rest of the three classes and got a grade above the average for all of them (at least for now). All the rest of my time was spent on this class and I do not even know if I could pass, I am considering not doing anything an just let it fail.
That is how bad this class is. When I was taking 35l I feel like it was hell, but now I would rather take another 10 quarter of 35l than taking one-quarter of this course. If you are looking for a class that is worse than cs35l, just take this class.
For cs35l it is possible to have a decent TA who could help you with the project. But for this class, TAs are NOT HELPFUL! Every time I ask about anything, he told me he did not know either. His lecture is basically reading the slides.
Lab 3 is extremely hard. More than half of the class did not finish it by the extended deadline. another thing which sucks about this class is, it requires special hardware that could only be accessed during the class, so if you can not figure it out during class time and office hours, you are doomed.
Overall, for this class, you get hard projects with a massive volume, little help from TA, little feedback from previous works, no extra resources to study. And the more you know software languages like java or python, the more you will probably be in trouble because hardware language works totally differently!
Finally, don't look at any comment that is earlier than mine. Because from this quarter they changed the requirement for the project. The project they used for last quarter is so easy compared to mine.
So, this class entirely depends on your TA. My TA was Hongxiang Gu. I think he's pretty fair in terms of grading the reports. It's good to start early. The guide they give about what the reports should be like definitely explain exactly what you need to write. We got 100% in all of the labs because we did the following:
- For every module, we described its functioning and name/explain how it interfaces with other modules and then drew a logic diagram
- For each module, we wrote something about how we tested it. If we didn't test it, we wrote a sentence or two about why we didn't (from a previous project, just looked if the hardware worked etc).
I think the TA just wanted a high level understanding of the architecture/design of the project.
My advice for the final project: Do not be too ambitious. Don't use a bunch of external hardware unless it's really well documented. Our project just used the FPGA board and the VGA output, we just added a bunch of features to make it good enough compared to the others.
Your grade depends on the curve, which sucks because it's a crapshoot depending on how good your class is.
Outside work: Me and my teammate did some of the coding/testbenches outside of lab, mainly because we were only 2 people. I know people who never needed to do work outside of lab.
I think the hardest lab was probably Lab 3, the stopwatch. To do well in that lab it's necessary to have a high level gameplan/design before you start coding. Make sure to use testbenches while you code, it's super useful for debugging and generally creating testbenches don't take too much time.
I got a raw score of 91.8% and got curved down to a B-. The other reviews are correct. This class is super BS. Although it is great being given the opportunity to write Verilog code in a more hands-on environment such as programming on an FPGA board, I learned nothing besides better Verilog programming. This class is just forgettable. I can even say this class is useless, considering you are not being rewarded for trying but rather create an artificial curve in a lab section as horrendous as physics labs. Got punished for trying very hard and doing well in the final project, but a few missteps and there goes your grade.
I am very very glad not that many classes are like this. I am just glad I passed this class in the 2 physics labs I have to take as a CSE major. This class is just terrible.
Pretty meh class. We did 4 projects using Verilog and fpga boards, and there was little instruction. Each project has a medium sized lab report component. The final project is open ended and worth 50% of your grade. The professor is not involved, so you better hope you get a cool TA like I had.
There is not enough lab time to complete the last project, so you need to go to several office hours to finish, which sucks.
Fairly easy and light class if you have decent lab partners.
The grading policy is unfortunately bullshit, with the average forced to a B- so everyone is curved down. We got >90% and got a B. The grading distributions of the past years no longer apply.
Based on 9 Users
TOP TAGS
- Participation Matters (3)
- Has Group Projects (4)
- Tolerates Tardiness (2)