Professor Sehat very clearly wants his students to learn the material and do well on the course. At times I felt it could be slightly hard to understand him but he was always more than happy to repeat and further explain any concepts.

This course isn't the heaviest course you'll take in terms of workload, but there is plenty to do and plenty to learn. Homework assignments would take me on average about two to three hours to complete and the projects about five to six. They (and the exams too) felt challenging but were at least interesting and in my opinion fun.

The one complaint I have about this class is how long it has taken (is taking) to get graded materials back. Professor Sehat releases previous years' graded homeworks and quizes and I would highly recommend looking at those before assignments and looking at the rubrics after assignments. I had thought I was doing well on the first few homeworks and first quiz, so I had not checked these but with the first quiz's grades released (the only graded material released as of week 10, including homeworks, projects, and quizes) it had turned out I had not understood the concepts as well as I thought. Still, professor Sehat always maintains that he is lenient with grading and that so long as we learn the material well, we can expect to recieve a good grade.

It really is a shame seeing/hearing most of the CS students in the classes being dragged through the course kicking and screaming, as the material is interesting, and despite what they might say, it seems the material is also potentially very useful as well.

All of the projects are coded in C++. If you are interested in doing projects in an HDL (verilog I believe), Professor Sehat has an honors section you can enroll in where you join a group and implement a riscv32 processor much like the one we learn in class on an FPGA. Course 183 I believe. Professor Sehat will mention it during lecture one, and while he will happily give PTE numbers if he can, note that the class will likely be full by week one.